ARA2004_11 Datasheet, PDF (13/21 Pages) ANADIGICS, Inc – Address-Programmable Reverse Amplifier with Step Attenuator

pARAMeteR
Table 8: Digital Interface Specification
Min
tYp
MAX
Logic High Input: VH
2.0
-
-
Logic Low Input: VL
-
-
0.8
Logic Input Current Consumption
-
-
0.01
Data to Clock Set Up Time: tCS
50
-
-
Data to Clock Hold Time: tCH
10
-
-
Clock Pulse Width High: tCWH
50
-
-
Clock Pulse Width Low: tCWL
50
-
-
Clock to Load Enable Setup
Time: tES
50
-
-
Load Enable Pulse Width: tEW
50
-
-
Rise Time: tR
-
10
-
Fall Time: tF
-
10
-
ARA2004
unit
V
V
mA
ns
ns
ns
ns
ns
ns
ns
ns
DATA
D₇ : MSB
D₆
D₄
D₃
D₁
D₀: LSB
CLOCK
ENABLE
OR
tCS
tCH
ENABLE
tCWL
tES
tCWH
tEW
Figure 17: Serial Data Input Timing
Data Sheet- Rev 2.2
13
04/2011