ARA2004_11 Datasheet, PDF (12/21 Pages) ANADIGICS, Inc – Address-Programmable Reverse Amplifier with Step Attenuator

ARA2004
LOGIC PROGRAMMING
Programming Instructions
The programming word is set through an 8 bit shift
register via the data, clock and enable lines. The data
is entered in order with the most significant bit (MSB)
first and the least significant bit (LSB) last. The enable
line must be low for the duration of the data entry, then
set high to latch the shift register. The rising edge of
the clock pulse shifts each data value into the register.
Software is Available from ANADIGICS Application
Engineering to set the data bits through the serial
cable on the ARA2004 evaluation board.
Table 6: Programming Register
DAtA Bit
D₇
D₆
D₅
D₄
D₃
D₂
D₁
D₀
function
P7
P6
P5
P4
P3
P2
P1
P0
Table 7: Data Description
VAlue
function
(1 = on, 0 = bypass)
P7
N/A
P6
N/A
P5
32 dB Atenuator Bit
P4
16 dB Attenuator Bit
P3
8 dB Attenuator Bit
P2
4 dB Attenuator Bit
P1
2 dB Attenuator Bit
P0
1 dB Attenuator Bit
12
Data Sheet- Rev 2.2
04/2011