TCS3472_17 Datasheet, PDF (23/40 Pages) ams AG – Red, Green, Blue (RGB), and Clear Light

TCS3472 − Register Description
Figure 27:
RGBC Timing Register
Fields Bits
ATIME
7:0
VALUE
0xFF
0xF6
0xD5
0xC0
0x00
RGBC Timing Register (0x01)
The RGBC timing register controls the internal integration time
of the RGBC clear and IR channel ADCs in 2.4-ms increments.
Max RGBC Count = (256 − ATIME) × 1024 up to a maximum of
65535.
Description
INTEG_CYCLES
1
TIME
2.4 ms
10
24 ms
42
101 ms
64
154 ms
256
700 ms
MAX COUNT
1024
10240
43008
65535
65535
Figure 28:
Wait Time Register
Wait Time Register (0x03)
Wait time is set 2.4 ms increments unless the WLONG bit is
asserted, in which case the wait times are 12× longer. WTIME is
programmed as a 2’s complement number.
Fields
WTIME
Bits
7:0
REGISTER VALUE
0xFF
0xAB
0x00
Description
WAIT TIME
1
85
256
TIME (WLONG= 0)
2.4 ms
204 ms
614 ms
TIME (WLONG= 1)
0.029 sec
2.45 sec
7.4 sec
ams Datasheet
[v1-02] 2016-Feb-08
Page 23
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