AMIS-30522 Datasheet, PDF (19/28 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522 Micro-stepping Motor Driver
Data Sheet
WRITE command executed for read-only register will not affect the register and the device operation. In case of READ command the
data byte is optional. If a byte is transmitted after READ command it is also interpreted as a command (see examples below).
If the master reads data from a status register (SPI Status Register Description), then the most significant bit (Data 7) represents a
parity of Data6 to Data0 bits. If the number of logical ones in the data is odd then the parity bit equals 1. If the number of logical ones
is even then the parity bit equals 0. This is a simple mechanism to protect against noise and to verify the correct transmission operation
and the consistency of the status data. If a parity check error occurs, the master could initiate an additional READ command to obtain
the status again.
The CSB line is active low and may remain low between each successive READ commands. There is only one exception of this rule: if
error condition is latched in status register (SPI Status Register Description) and the master needs to clear the status bits then exactly
after READ command of a latched status register CSB line should go from low to high. This is explained in the following note:
Note: The status registers and ERRB pin (SPI Status Register Description) are updated by the internal system clock
only when CSB line is high. It is recommended to keep the CSB line high always when the SPI bus is idle.
If the master sends WRITE command, then the incoming data will be stored in the corresponding register only if CSB goes from low to
high. The writing to the register is only enabled if exactly 16 bits are transmitted within one transfer packet. If more or less clock pulses
are counted within one packet the complete packet is ignored.
AMIS-30522 responds on every incoming byte by shifting out the data stored on the last address sent via the bus. After POR the initial
address is unknown. The following examples illustrate communication sessions between the master and AMIS-30522:
CSB
Master
305xx
AddrA
Read
Last Addr
Data
AddrB
Write
AddrA
DataA
DataC
AddrB
DataB
AddrB
Read
AddrB
DataB
AddrB
Read
AddrB
DataC
DataC is written in AddrB on
rising edge of CSB
Figure 17: Example SPI Transfer
In this example, the master reads first the status from AddrA and then writes control byte in AddrB. After write operation the master
could initiate a read back command in order to verify the data just written. Note that the first verification read operation returns the old
content of AddrB, the second read command returns the new AddrB data.
Note: The internal data out shift buffer of AMIS-30522 is updated with the content of the selected SPI register only at
the last (every eighth) falling edge of the CLK signal (SPI Transfer Format and Pin Signals). As a result, new data for
transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out
might represent old data.
This rule also applies when the master device wants to initiate an SPI transfer to read the status registers. Because the internal system
clock updates the status registers only when CSB line is high, the first read out byte might represent an old status (see Figure 18 and
Figure 19).
AMI Semiconductor – June 2007, M-20684-001
19
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