AMIS-30522 Datasheet, PDF (15/28 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522 Micro-stepping Motor Driver
Data Sheet
Table 30: SPI Status Register 1 and (Table 31: SPI Status Register 2 (<OVCXij> and <OVCYij>). Error condition is latched and the
microcontroller needs to clean the status bits to reactivate the drivers.
8.6.3. Open Coil Detection
Open coil detection is based on the observation of 100 percent duty cycle of the PWM regulator. If in a coil 100 percent duty cycle is
detected for longer than 200ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI
status register is set (<OPENX> or <OPENY>). (Table 29: SPI Status Register 0)
8.6.4. Charge Pump Failure
The charge pump is an important circuit that guarantees low Rdson for all drivers, especially for low supply voltages. If supply voltage
is too low or external components are not properly connected to guarantee Rdson of the drivers, then the bit <CPFAIL> is set in Table
29: SPI Status Register 0. Also after POR the charge pump voltage will need some time to exceed the required threshold. During that
time <CPFAIL> will be set to “1”.
8.6.5. Error Output
This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination
of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR < OVCYij> OR <OPENi> OR <CPFAIL>
8.7 Logic Supply Regulator
AMIS-30522 has an on-chip 5V low-drop regulator with external capacitor to supply the digital part of the chip, some low-voltage analog
blocks and external circuitry. The voltage is derived from an internal bandgap reference. To calculate the available drive-current for
external circuitry, the specified I_load should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads
connected to logic outputs. See Table 5.
8.8 Power-On Reset (POR) Function
The open drain output pin PORB/WD provides an “active low” reset for external purposes. At power-up of AMIS-30522, this pin will be
kept low for some time to reset for example an external microcontroller. A small analog filter avoids resetting due to spikes or noise on
the VDD supply.
VBB
VDD
tPU
t
tPD
VDDH
VDDL
t
< tRF
POR/WD pin
tPOR
tRF
PC20070604.8
Figure 14: Power-on-Reset Timing Diagram
8.9 Watchdog Function
The watchdog function is enabled/disabled through <WDEN> bit (Table 14: SPI Control Register WR). Once this bit has been set to “1”
(watchdog enable), the microcontroller needs to re-write this bit to clear an internal timer before the watchdog timeout interval expires.
AMI Semiconductor – June 2007, M-20684-001
15
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