ELANSC520 Datasheet, PDF (95/440 Pages) Advanced Micro Devices – Microcontroller

SDRAM Controller Registers
SDRAM Bank 0–3 Ending Address (DRCBENDADR)
Memory-Mapped
MMCR Offset 18h
31
30
29
28
27
26
25
24
Bit BNK3_ENB
BNK3_END[28–22]
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Bit BNK2_ENB
BNK2_END[28–22]
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit BNK1_ENB
BNK1_END[28–22]
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit BNK0_ENB
BNK0_END[28–22]
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
Register Description
This register controls the SDRAM bank enable and bank ending address that specifies the boundary between the
banks.
Note: A programmable reset preserves this register’s state.See the PRG_RST_ENB bit description on page 3-3.
Bit Definitions
Bit Name
31
BNK3_ENB
30–24 ^BNK3_END
[28–22]
23
BNK2_ENB
Function
Bank 3 Enable
This bit enables Bank 3.
0 = Disabled
1 = Enabled
Bank 3 Ending Address
This bit field determines the Bank 3 boundary, defined in 4-Mbyte increments. This value is
compared to physical address bits 28–22 during an SDRAM request to select a bank.
Bank 3 is selected if physical address bits 28–22 are less than the BNK3_END bit field value,
but greater than or equal to the value specified by the BNK2_END bit field (or the next lower
enabled bank’s end value if Bank 2 is disabled).
Bank 2 Enable
This bit enables Bank 2.
0 = Disabled
1 = Enabled
Élan™SC520 Microcontroller Register Set Manual
7-7