ELANSC520 Datasheet, PDF (88/440 Pages) Advanced Micro Devices – Microcontroller

PCI Bus Host Bridge Registers
Master Retry Time-Out (PCIMRETRYTO)
I/O Address 0CF8h/0CFCh
PCI Index 41h
7
6
5
4
3
2
1
0
Bit
M_RETRY_TO[7–0]
Reset
0
0
0
0
0
0
0
0
R/W
R
Register Description
This register contains the PCI master retry time-out.
Bit Definitions
Bit Name
Function
7–0 ^{M_RETRY_TO Master Retry Time-Out}
[7–0]
This bit field defines the number of times the master controller retries a transaction before
aborting the cycle. For read transactions that are aborted due to a time-out, a data value of
FFFFFFFFh is returned to the Am5_x86 CPU.
00h = Retry time-out disabled. The master controller continues to retry the transaction until
the target responds. This is the default value.
Other = The master controller continues to retry the transaction for the number of times
programmed into this bit field. For example, if this bit field is set to 80h, the number of
retries is 128. Therefore the total number of attempts (including the initial attempt) is
the number of retries programmed in this bit field plus 1.
Programming Notes
This register is reset by a system reset or by a PCI bus reset. A PCI bus reset is initiated by setting the PCI_RST
bit in the HBCTL register (see page 6-3).
This register (PCIMRETRYTO) is byte 1 of register number 16d in the host bridge-specific PCI configuration space.
This register must not be changed except when there is no outstanding CPU-to-PCI bus transaction pending. This
is the default state after a system reset. See the Élan™SC520 Microcontroller User’s Manual, order #22004, for
information about PCI bus initialization.
6-24
Élan™SC520 Microcontroller Register Set Manual