SC3200 Datasheet, PDF (73/447 Pages) Advanced Micro Devices – AMD GEODE-TM SC3200 PROCESSOR

Signal Definitions
Revision 5.1
3.4.7 Sub-ISA Interface Signals
Ball No.
Signal Name
A[23:0]
D15
D14
D13
D12
D11
D10
D9
D8
D[7:0]
BHE#
IOCS1#
IOCS0#
ROMCS#
DOCCS#
TRDE#
RD#
WR#
IOR#
IOW#
DOCR#
DOCW#
EBGA TEPBGA Type Description
See
Table 3-3
on page
38.
See
Table 3-3
on page
38.
See
Table 3-5
on page
54.
See
Table 3-5
on page
54.
O Address Lines
I/O Data Bus
B5
E4
H2
D10
AL12
N30
J4
A10
G4
C30
H3
A9
AJ13
N31
H1
D11
F3
B8
G1
B9
F1
D9
G3
A8
F1
D9
G3
A8
O Byte High Enable. With A0, defines byte
accessed for 16 bit wide bus cycles.
O I/O Chip Selects
O ROM or Flash ROM Chip Select
O DiskOnChip or NAND Flash Chip Select
O Transceiver Data Enable Control. Active
low for Sub-ISA data transfers. The signal
timing is as follows:
• In a read cycle, TRDE# has the same
timing as RD#.
• In a write cycle, TRDE# is asserted (to
active low) at the time WR# is asserted. It
continues being asserted for one PCI
clock cycle after WR# has been negated,
then it is negated.
O Memory or I/O Read. Active on any read
cycle.
O Memory or I/O Write. Active on any write
cycle.
O I/O Read. Active on any I/O read cycle.
O I/O Write. Active on any I/O write cycle.
O DiskOnChip or NAND Flash Read. Active
on any memory read cycle to DiskOnChip.
O DiskOnChip or NAND Flash Write. Active
on any memory write cycle to DiskOnChip.
Mux
AD[23:0]
STOP#
IRDY#
TRDY#
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD[31:24]
DEVSEL#
GPIO1+TFTD12
AB1D+GPIO1
GPIO17+TFTDCK
BOOT16 (Strap)
GPIO20+TFTD0
AB1C+GPIO20
GPIO0
CLKSEL0 (Strap)
---
DOCR#+GPIO14
DOCW#+GPIO15
IOR#+GPIO14
IOW#+GPIO15
AMD Geode™ SC3200 Processor Data Book
73