SC3200 Datasheet, PDF (68/447 Pages) Advanced Micro Devices – AMD GEODE-TM SC3200 PROCESSOR

Revision 5.1
Signal Definitions
3.4.6 PCI Bus Interface Signals
BalL No.
Signal Name
EBGA TEPBGA Type Description
Mux
PCICLK
PCICLK0
PCICLK1
AD[31:24]
AD[23:0]
C/BE3#
C/BE2#
C/BE1#
C/BE0#
INTA#
INTB#
INTC#
INTD#
E2
A7
I PCI Clock. PCICLK provides timing for all
---
transactions on the PCI bus. All other PCI
signals are sampled on the rising edge of
PCICLK, and all timing parameters are
defined with respect to this edge.
D3
A4
O PCI Clock Outputs. PCICLK0 and PCICLK1 FPCI_MON (Strap)
E4
D6
O
provide clock drives for the system at 33
MHz. These clocks are asynchronous to PCI
LPC_ROM (Strap)
signals. There is low skew between all out-
puts. One of these clock signals should be
connected to the PCICLK input. All PCI clock
users in the system (including PCICLK)
should receive the clock with as low a skew
as possible.
See
Table 3-3
on page
38.
See
Table 3-5
on page
54.
I/O Multiplexed Address and Data. A bus
transaction consists of an address phase in
the cycle in which FRAME# is asserted fol-
lowed by one or more data phases. During
the address phase, AD[31:0] contain a physi-
cal 32-bit address. For I/O, this is a byte
address. For configuration and memory, it is
a DWORD address. During data phases,
AD[7:0] contain the least significant byte
(LSB) and AD[31:24] contain the most signifi-
cant byte (MSB).
D[7:0]
A[23:0]
A8
H4
I/O Multiplexed Command and Byte Enables.
D11
D8
F3
During the address phase of a transaction
when FRAME# is active, C/BE[3:0]# define
D10
A10
J2
the bus command. During the data phase, C/
D9
A13
L1
BE[3:0]# are used as byte enables. The byte
D8
enables are valid for the entire data phase
and determine which byte lanes carry mean-
ingful data. C/BE0# applies to byte 0 (LSB)
and C/BE3# applies to byte 3 (MSB).
AE3
D26
I PCI Interrupts. The SC3200 provides inputs
---
AF1
C26
for the optional “level-sensitive” PCI inter-
rupts (also known in industry terms as
---
H4
C9
PIRQx#). These interrupts can be mapped to GPIO19+IOCHRDY
B22
AA2
IRQs of the internal 8259A interrupt control-
lers using PCI Interrupt Steering Registers 1
IDE_DATA7
and 2 (F0 Index 5Ch and 5Dh).
Note: If selected as INTC# or INTD# func-
tion(s) but not used, tie INTC# and
INTD# high.
68
AMD Geode™ SC3200 Processor Data Book