SC3200 Datasheet, PDF (167/447 Pages) Advanced Micro Devices – AMD GEODE-TM SC3200 PROCESSOR

Core Logic Module
6.2.5.6 ROM Interface
The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap deter-
mines the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block (see Table 4-2 on page 88 for
bit details) allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#, WR# and ROMCS#
asserted.
6.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing
The SC3200 multiplexes most PCI and Sub-ISA signals on
the balls listed in Table 6-3, in order to reduce the number
of balls on the device. Cycle multiplexing is on a bus-cycle
by bus-cycle basis (see Figure 6-6 on page 168), where
the internal Core Logic PCI bridge arbitrates between PCI
cycles and Sub-ISA cycles. Other PCI and Sub-ISA signals
remain non-shared, however, some Sub-ISA signals may
be muxed with GPIO.
Sub-ISA cycles are only generated as a result of GX1 mod-
ule accesses to the following addresses or conditions:
• ROMCS# address range.
• DOCCS# address range.
• IOCS0# address range.
• IOCS1# address range.
• An I/O write to address 80h or to 84h.
• Internal ISA is programmed to be the subtractive decode
agent and no other agents claim the cycle.
If the Sub-ISA and PCI bus have more than four compo-
nents, the Sub-ISA components can be buffered using
74HCT245 or 74FCT245 type transceivers. The RD# (an
AND of IOR#, MEMR#) signal can be used as DIR control
while TRDE# is used as enable control.
Revision 5.1
Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls
Ball No.
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PAR
TRDY#
IRDY#
STOP#
DEVSEL#
Sub-ISA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
BHE#
EBGA
A17
D16
A18
A15
A16
A14
C15
B14
C14
B13
C13
C12
A12
C11
A11
B10
A7
C7
D7
A6
D6
C6
A5
F4
C5
D5
A4
B4
C4
A3
C2
B3
A13
A10
D8
A8
C10
B8
C8
D9
B5
TEPBGA
U1
P3
U3
N1
P1
N3
N2
M2
M4
L2
L3
K1
L4
J1
K4
J3
E1
F4
E3
E2
D3
D1
D2
B6
C2
C4
C1
D4
B4
B3
A3
D5
L1
J2
F3
H4
J4
F1
F2
G1
E4
AMD Geode™ SC3200 Processor Data Book
167