SC3200 Datasheet, PDF (59/447 Pages) Advanced Micro Devices – AMD GEODE-TM SC3200 PROCESSOR

Signal Definitions
Revision 5.1
3.3 Multiplexing Configuration
The tables that follow list multiplexing options and their
configurations. Certain multiplexing options may be chosen
per signal; others are available only for a group of signals.
Where ever a GPIO pin is multiplexed with another func-
tion, there is an optional pull-up resistor on this pin; after
system reset, the pull-up is present. This pull-up resistor
can be disabled by writing Core Logic registers. The con-
figuration is without regard to the selected ball function.
The above applies to all pins multiplexed with GPIO,
except GPIO12, GPIO13, and GPIO16.
Table 3-7. Two-Signal/Group Multiplexing
Default
Alternate
EBGA TEPBGA
Signal
Configuration
Signal
Configuration
Ball No.
A26
AD3
C26
AE1
C17
U2
B24
AC3
A24
AC1
D23
AC2
C23
AB4
B23
AB1
A23
AA4
C22
AA3
B22
AA2
A21
Y3
C20
Y2
A20
Y1
C19
W4
B19
W3
A19
V3
C18
V2
B18
V1
C21
Y4
A25
AD1
C24
AC4
D24
AD2
A27
AF2
C16
P2
C25
AD4
A22
AA1
D25
AF1
Ball No.
H1
D11
IDE_ADDR0
IDE_ADDR1
IDE_ADDR2
IDE_DATA0
IDE_DATA1
IDE_DATA2
IDE_DATA3
IDE_DATA4
IDE_DATA5
IDE_DATA6
IDE_DATA7
IDE_DATA8
IDE_DATA9
IDE_DATA10
IDE_DATA11
IDE_DATA12
IDE_DATA13
IDE_DATA14
IDE_DATA15
IDE_IOR0#
IDE_IORDY0
IDE_DREQ0
IDE_IOW0#
IDE_CS0#
IDE_CS1#
IDE_DACK0#
IDE_RST#
IRQ14
TRDE#
IDE
PMR[24] = 0
Sub-ISA
PMR[12] = 0
TFT, PCI, GPIO, System
TFTD3
TFTD2
TFTD4
TFTD6
TFTD16
TFTD14
TFTD12
FP_VDD_ON
CLK27M
IRQ9
INTD#
GPIO40
DDC_SDA
DDC_SCL
GPIO41
TFTD13
TFTD15
TFTD17
TFTD7
TFTD10
TFTD11
TFTD8
TFTD9
TFTD5
TFTDE
TFTD0
TFTDCK
TFTD1
PMR[24] = 1
GPIO
GPIO0
PMR[12] = 1
AMD Geode™ SC3200 Processor Data Book
59