PALCE16V8 Datasheet, PDF (4/26 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic

FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. It has eight
independently configurable macrocells (MC0–MC7).
Each macrocell can be configured as registered output,
combinatorial output, combinatorial I/O or dedicated in-
put. The programming matrix implements a program-
mable AND logic array, which drives a fixed OR logic
array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal po-
larity. Pins 1 and 11 serve either as array inputs or as
clock (CLK) and output enable (OE), respectively, for all
flip-flops.
Unused input pins should be tied directly to VCC or GND.
Product terms with all bits unprogrammed (discon-
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are
automatically configured from the user’s design
11
0X
10
AMD
specification. The design specification is processed by
development software to verify the design and create a
programming file (JEDEC). This file, once downloaded
to a programmer, configures the device according to the
user’s desired function.
The user is given two design options with the
PALCE16V8. First, it can be programmed as a standard
PAL device from the PAL16R8 and PAL10H8 series.
The PAL programmer manufacturer will supply device
codes for the standard PAL device architectures to be
used with the PALCE16V8. The programmer will pro-
gram the PALCE16V8 in the corresponding architec-
ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed as
a PALCE16V8. Here the user must use the PALCE16V8
device code. This option allows full utilization of the
macrocell.
11
OE
10
VCC
00
01
To
Adjacent
Macrocell
SG1
SL0 _X
SL1X
11
0X
DQ
10
CLK
Q
10
11
0X
* SG1
SL0X
*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
PALCE16V8 Macrocell
I/OX
From
Adjacent
Pin
16493D-4
PALCE16V8 Family
2-39