PALCE16V8 Datasheet, PDF (24/26 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic

ROBUSTNESS FEATURES
PALCE16V8X-X/5 devices have some unique features
that make them extremely robust, especially when oper-
ating in high-speed design environments. Pull-up resis-
tors on inputs and I/O pins cause unconnected pins to
default to a known state. Input clamping circuitry limits
negative overshoot, eliminating the possibility of false
AMD
clocking caused by subsequent ringing. A special noise
filter makes the programming circuitry completely insen-
sitive to any positive overshoot that has a pulse width of
less than about 100 ns for the /5 versions. Selected /4
devices are also being retrofitted with these robustness
features. See chart below for device listings.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSIONS AND SELECTED /4
VERSIONS*
VCC
VCC
> 50 kΩ
ESD
Protection
and
Clamping
Programming
Pins only
Programming
Voltage
Detection
Typical Input
Positive
Overshoot
Filter
Programming
Circuitry
VCC
VCC
> 50 kΩ
Provides ESD
Protection and
Clamping
Preload Feedback
Circuitry Input
Typical Output
16493D-14
*
Rev Letter
Device
Filter Only Filter and Pullups
PALCE16V8H-10
E, F, K
L
PALCE16V8H-15 D, E, F, G, I, J, K
L, M
PALCE16V8Q-15
D, G, J
M
Topside Marking:
AMD CMOS PLD’s are marked on the top of the package in the
following manner:
PALCEXXXX
Date Code (3 numbers) Lot ID (4 characters)– –(Rev. Letter)
PALCE16V8H-25
D, G, J
M
The Lot ID and Rev Letter are separated by two spaces.
PALCE16V8Q-25
D, G, J
M
PALCE16V8 Family
2-59