PALCE16V8 Datasheet, PDF (1/26 Pages) Advanced Micro Devices – EE CMOS 20-Pin Universal Programmable Array Logic

FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/25, Q-20/25
PALCE16V8 Family
EE CMOS 20-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Pin and function compatible with all 20-pin
GAL devices
s Electrically erasable CMOS technology
provides reconfigurable logic and full
testability
s High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
s Direct plug-in replacement for the PAL16R8
series and most of the PAL10H8 series
s Outputs programmable as registered or
combinatorial in any combination
s Peripheral Component Interconnect (PCI)
compliant
s Programmable output polarity
s Programmable enable/disable control
s Preloadable output registers for testability
s Automatic register reset on power up
s Cost-effective 20-pin plastic DIP, PLCC, and
SOIC packages
s Extensive third-party software and programmer
support through FusionPLD partners
s Fully tested for 100% programming and
functional yields and high reliability
s 5 ns version utilizes a split leadframe for
improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocells provide a universal device
architecture. The PALCE16V8 will directly replace the
PAL16R8 and PAL10H8 series devices, with the excep-
tion of the PAL16C1.
The PALCE16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial with an active-
high or active-low output. The output configuration is
determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
AMD’s FusionPLD program allows PALCE16V8 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
2-36
Publication# 16493 Rev. D Amendment /0
Issue Date: February 1996