ARRIAGX_09 Datasheet, PDF (99/234 Pages) Altera Corporation – The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers

Chapter 2: Arria GX Architecture
2–93
I/O Structure
f For the specific sustaining current driven through this resistor and overdrive current
used to identify the next-driven input level, refer to the DC & Switching Characteristics
chapter.
Programmable Pull-Up Resistor
Each Arria GX device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 k) holds the output to the V_CCIO level of the output pin’s bank.
Advanced I/O Standard Support
Arria GX device IOEs support the following I/O standards:
■ 3.3-V LVTTL/LVCMOS
■ 2.5-V LVTTL/LVCMOS
■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
■ 3.3-V PCI
■ 3.3-V PCI-X mode 1
■ LVDS
■ LVPECL (on input and output clocks only)
■ Differential 1.5-V HSTL class I and II
■ Differential 1.8-V HSTL class I and II
■ Differential SSTL-18 class I and II
■ Differential SSTL-2 class I and II
■ 1.2-V HSTL class I and II
■ 1.5-V HSTL class I and II
■ 1.8-V HSTL class I and II
■ SSTL-2 class I and II
■ SSTL-18 class I and II
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1