ARRIAGX_09 Datasheet, PDF (180/234 Pages) Altera Corporation – The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers

4–58
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 4 of 4)
I/O Standard
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
3.3-V PCI
Drive
Strength
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
—
3.3-V PCI-X
—
LVDS
—
Clock
Parameter
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
GCLK
t_CO
GCLK PLL
t_CO
Fast Corner
Industrial
2.602
1.164
2.604
1.166
2.604
1.166
2.637
1.196
2.644
1.206
2.626
1.188
2.626
1.188
2.620
1.182
2.607
1.169
2.610
1.172
2.612
1.174
2.786
1.322
2.786
1.322
3.621
2.190
Commercial
2.602
1.164
2.604
1.166
2.604
1.166
2.637
1.196
2.644
1.206
2.626
1.188
2.626
1.188
2.620
1.182
2.607
1.169
2.610
1.172
2.612
1.174
2.786
1.322
2.786
1.322
3.621
2.190
–6 Speed
Grade
5.574
2.314
5.578
2.325
5.577
2.334
5.675
2.569
5.651
2.554
5.653
2.556
5.655
2.558
5.653
2.556
5.573
2.368
5.571
2.378
5.581
2.391
5.803
2.697
5.803
2.697
6.969
3.880
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4–64 through Table 4–65 list EP1AGX50 regional clock (RCLK) adder values that
should be added to the GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation