ARRIAGX_09 Datasheet, PDF (49/234 Pages) Altera Corporation – The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers

Chapter 2: Arria GX Architecture
2–43
Adaptive Logic Modules
Figure 2–38. Register Chain within a LAB (Note 1)
Combinational
Logic
adder0
adder1
reg_chain_in
From Previous ALM
Within The LAB
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
Combinational
Logic
adder0
adder1
DQ
reg0
To general or
local routing
To general or
local routing
DQ
reg1
To general or
local routing
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–38:
(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register ’s clear and load/preset signals. The
ALM directly supports an asynchronous clear and preset function. The register preset
is achieved through the asynchronous load of a logic high. The direct asynchronous
preset does not require a NOT gate push-back technique. Arria GX devices support
simultaneous asynchronous load/preset and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one load/preset signal.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1