ARRIAGX_09 Datasheet, PDF (226/234 Pages) Altera Corporation – The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers

4–104
Chapter 4: DC and Switching Characteristics
PLL Timing Specifications
Table 4–116. Enhanced PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
t_{REC ONFIGWAI T}
The time required for the wait after the
reconfiguration is done and the areset is
applied.
—
—
Notes to Table 4–116:
(1) This is limited by the I/O f_MAX.
(2) If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.
Table 4–117. Fast PLL Specifications (Part 1 of 2)
Name
Description
Min
Typ
Max
f_IN
Input clock frequency 16.08
—
640
f_INPFD
Input frequency to the
PFD
16.08
—
500
f_INDUTY
t_INJITTER
Input clock duty cycle
40
—
60
Input clock jitter
tolerance in terms of
period jitter.
—
0.5
—
Bandwidth 2 MHz
Input clock jitter
tolerance in terms of
period jitter.
—
1.0
—
Bandwidth  0.2 MHz
Upper VCO frequency
range
300
—
840
f_VCO
Lower VCO frequency
range
150
—
420
PLL output frequency
to GCLK or RCLK
4.6875
—
550
f_OUT
PLL output frequency
to LVDS or DPA clock
150
—
840
f_{OUT_ EX T}
PLL clock output
frequency to regular 4.6875
—
(1)
I/O
t_CONFIGPLL
Time required to
reconfigure scan
—
75/f_SCANCLK
—
chains for fast PLLs
f_CLBW
PLL closed-loop
bandwidth
1.16
5
28
Time required for the
PLL to lock from the
t_{L OC K}
time it is enabled or
—
0.03
1
the end of the device
configuration
t_{PLL_PSERR}
Accuracy of PLL phase
shift
—
—
±30
t_ARESET
Minimum pulse width
on areset signal.
10
—
—
Max
Units
2
us
Units
MHz
MHz
%
ns (p-p)
ns (p-p)
MHz
MHz
MHz
MHz
MHz
ns
MHz
ms
ps
ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation