EPC16QI100N Datasheet, PDF (8/36 Pages) Altera Corporation – This datasheet describes enhanced configuration (EPC) devices

Page 8
Functional Description
FPGA Configuration
FPGA configuration is managed by the configuration controller chip. This process
includes reading configuration data from the flash memory, decompressing the
configuration data, transmitting configuration data using the appropriate DATA[]
pins, and handling error conditions.
After POR, the controller determines the user-defined configuration options by
reading its option bits from the flash memory. These options include the configuration
scheme, configuration clock speed, decompression, and configuration page settings.
The option bits are stored at flash address location 0x8000 (word address) and occupy
512-bits or 32-words of memory. These options bits are read using the internal flash
interface and the default 10 MHz internal oscillator.
After obtaining the configuration settings, the configuration controller chip checks if
the FPGA is ready to accept configuration data by monitoring the nSTATUS and
CONF_DONE signals. When the FPGA is ready (nSTATUS is high and CONF_DONE is low),
the controller begins data transfer using the DCLK and DATA[] output pins. The
controller selects the configuration page to be transmitted to the FPGA by sampling
its PGM[2..0] pins after POR or reset.
The function of the configuration unit is to transmit decompressed data to the FPGA,
depending on the configuration scheme. The EPC device supports four concurrent
configuration modes, with n = 1, 2, 4, or 8 (where n is the number of bits that are sent
per DCLK cycle on the DATA[n] signals). The value n = 1 corresponds to the traditional
PS configuration scheme. The values n = 2, 4, and 8 correspond to concurrent
configuration of 2, 4, or 8 different PS configuration chains, respectively. Additionally,
the FPGA can be configured in FPP mode, where eight bits of DATA are clocked into
the FPGA per DCLK cycle. Depending on the configuration bus width (n), the circuit
shifts uncompressed configuration data to the valid DATA[n] pins. Unused DATA[]
pins drive low.
In addition to transmitting configuration data to the FPGAs, the configuration circuit
is also responsible for pausing configuration whenever there is insufficient data
available for transmission. This occurs when the flash read bandwidth is lower than
the configuration write bandwidth. Configuration is paused by stopping the DCLK to
the FPGA, when waiting for data to be read from the flash or for data to be
decompressed. This technique is called “Pausing DCLK”.
The EPC device flash-memories feature a 90-ns access time (approximately 10 MHz).
Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps)
(16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported
by Altera FPGAs are much higher and translate to high configuration write
bandwidths. For example, 100-MHz Stratix FPP configuration requires data at the rate
of 800 Mbps (8-bit DATA[] bus at 100 MHz). This is much higher than the 160 Mbps the
flash memory can support and is the limiting factor for configuration time.
Compression increases the effective flash-read bandwidth as the same amount of
configuration data takes up less space in the flash memory after compression. Since
Stratix configuration data compression ratios are approximately two, the effective
read bandwidth doubles to about 320 Mbps.
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation