EPC16QI100N Datasheet, PDF (29/36 Pages) Altera Corporation – This datasheet describes enhanced configuration (EPC) devices

Timing Information
Page 29
Table 13. JTAG Timing Parameters and Values (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
t_JPXZ
JTAG port valid output to high impedance
—
25
ns
t_JSSU
Capture register setup time
20
—
ns
t_JSH
Capture register hold time
45
—
ns
t_JSCO
Update register clock to output
—
25
ns
t_JSZX
Update register high-impedance to valid output
—
25
ns
t_JSXZ
Update register valid output to high impedance
—
25
ns
Timing Information
Figure 7 shows the configuration timing waveform when you are using an EPC
device.
Figure 7. Configuration Timing Waveform Using an EPC Device
nINIT_CONF or VCC/nCONFIG
t_POR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA[7..0]
t_OEZX
User I/O
INIT_DONE
t_DSU t_CL
t_CH
t_DH
Byte0 Byte1 Byte2 Byte3
t_CO
Tri-State
Notes to Figure 7:
(1) The EPC device drives DCLK low after configuration.
(2) The EPC device drives DATA[] high after configuration.
Byten
Tri-State
(2)
User Mode
Table 14 lists the timing parameters when you are using the EPC devices.
Table 14. EPC Device Configuration Parameters (Part 1 of 2)
Symbol
f_DCLK
t_DCLK
t_HC
t_LC
t_CE
t_OE
t_OH
t_CF ⁽²⁾
t_DF ⁽²⁾
t_RE ⁽³⁾
t_LOE
f_ECLK
Parameter
DCLK frequency
DCLK period
DCLK duty cycle high time
DCLK duty cycle low time
OE to first DCLK delay
OE to first DATA available
DCLK rising edge to DATA change
OE assert to DCLK disable delay
OE assert to DATA disable delay
DCLK rising edge to OE
OE assert time to assure reset
EXCLK input frequency
Condition
Min
Typ
Max
Unit
40% duty cycle
—
—
66.7 MHz
—
15
—
—
ns
40% duty cycle
6
—
—
ns
40% duty cycle
6
—
—
ns
—
40
—
—
ns
—
40
—
—
ns
—
(1)
—
—
ns
—
277
—
—
ns
—
277
—
—
ns
—
60
—
—
ns
—
60
—
—
ns
40% duty cycle
—
—
100
MHz
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet