EPC16QI100N Datasheet, PDF (12/36 Pages) Altera Corporation – This datasheet describes enhanced configuration (EPC) devices

Page 12
Functional Description
Figure 3 shows the schematic for configuring multiple FPGAs concurrently in the PS
mode using an EPC device.
Figure 3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
n
(6)
N.C.
n
(6)
N.C.
n
(6)
N.C.
VCC (1) VCC (1)
EPC Device
FPGA0
(3)
DCLK
DATA0
MSEL
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
MSEL
FPGA1
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
MSEL
nCEO
FPGA7
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
(3)
WE#C
RP#C
WE#F
DCLK
RP#F
DATA0
A[20..0]
N.C.
RY/BY#
N.C.
DATA1
CE#
N.C.
OE#
N.C.
OE (3)
DQ[15..0]
N.C.
nCS (3)
nINIT_CONF (2)
DATA 7
(1)
V_CC
WP#
BYTE# (5)
TM1
VCCW
PORSEL
PGM[2..0]
EXCLK
V_CC (7)
(4)
(4)
(4)
TMO
GND
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 3:
(1) Connect V_CC to the same supply voltage as the EPC device.
(2) The nINIT_CONF pin is available on EPC devices and has an internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the nINIT_CONF or nCONFIG signal. The nINIT_CONF pin does not need to be connected if its functionality is not
used. If nINIT_CONF is not used, nCONFIG must be pulled to V_CC either directly or through a resistor.
(3) The EPC devices’ OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors
should not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 10 on page 24.
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1to F-A1, C-A15 to F-A15, C-A16 to F-A16,
and BYTE# to V_CC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP# to F-
RP#, C-WE# to F-WE#, TM1 to V_CC, TM0 to GND, and WP# to V_CC.
(6) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For more information, refer to the configuration chapter in the
appropriate device handbook.
(7) To protect Intel Flash based EPC devices content, isolate the V_CCW supply from V_CC. For more information, refer to “Intel Flash-Based EPC Device
Protection” on page 16.
Enhanced Configuration (EPC) Devices Datasheet
January 2012 Altera Corporation