EPC16QI100N Datasheet, PDF (17/36 Pages) Altera Corporation – This datasheet describes enhanced configuration (EPC) devices

Functional Description
Page 17
If an external power up monitoring circuit is connected to the RP# pin with the
loop-back connection, use the following guidelines to avoid contention on the RP#
line:
■ The power-up sequence on the 3.3-V supply should complete within 50 ms of
power up. The 3.3-V V_CC should reach the minimum V_CC before 50 ms and RP#
should then be released.
■ RP# should be driven low by the power-up monitoring circuit during power up.
After power up, RP# should be tri-stated externally by the power-up monitoring
circuit.
If the preceding guidelines cannot be completed within 50 ms, then the OE pin must be
driven low externally until RP# is ready to be released.
Dynamic Configuration (Page Mode)
The dynamic configuration (or page mode) feature allows the EPC device to store up
to eight different sets of designs for all the FPGAs in your system. You can then
choose which page (set of configuration files) the EPC device should use for FPGA
configuration.
Dynamic configuration or the page mode feature enables you to store a minimum of
two pages—a factory default or fail-safe configuration and an application
configuration. The fail-safe configuration page could be programmed during system
production, while the application configuration page could support remote or local
updates. These remote updates could add or enhance system features and
performance. However, with remote update capabilities comes the risk of possible
corruption of configuration data. In the event of such a corruption, the system could
automatically switch to the fail-safe configuration and avoid system downtime.
The EPC device page mode feature works with the Stratix remote system
configuration feature, to enable intelligent remote updates to your systems.
f For more information about remotely updating Stratix FPGAs, refer to the Remote
System Configuration with Stratix & Stratix GX Devices chapter in the Stratix Device
Handbook.
The three PGM[2..0] input pins control which page is used for configuration and these
pins are sampled at the start of each configuration cycle when OE goes high. The page
mode selection allows you to dynamically reconfigure the functionality of your FPGA
by switching the PGM[2..0] pins and asserting nCONFIG. Page 0 is defined as the
default page and the PGM[2] pin is the MSB.
1 The PGM[2..0] input pins must not be left floating on your board. When you are not
using this feature, connect the PGM[2..0] pins to GND to select the default page 000.
The EPC device pages are dynamically-sized regions in memory. The start address
and length of each page is programmed into the option-bit space of the flash memory
during initial programming. All subsequent configuration cycles sample the PGM[]
pins and use the option-bit information to jump to the start of the corresponding
configuration page. Each page must have configuration files for all FPGAs in your
system that are connected to that EPC device.
January 2012 Altera Corporation
Enhanced Configuration (EPC) Devices Datasheet