PC28F512G18FF Datasheet, PDF (73/118 Pages) Micron Technology – 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory

AC Write Specifications
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
AC Write Specifications
Table 41: AC Write Specifications
Notes 1 and 2 apply to all
Parameter
Symbol
RST# HIGH recovery to WE# LOW
t_PHWL
CE# setup to WE# LOW
t_ELWL
WE# write pulse width LOW
t_WLWH
Data setup to WE# HIGH
t_DVWH
Address setup to WE# HIGH
t_AVWH
CE# hold from WE# HIGH
t_WHEH
Data hold from WE# HIGH
t_WHDX
Address hold from WE# HIGH
t_WHAX
WE# pulse width HIGH
t_WHWL
V_PP setup to WE# HIGH
V_PP hold from status read
WP# hold from status read
t_VPWH
t_QVVL
t_QVBL
WP# setup to WE# HIGH
t_BHWH
WE# HIGH to OE# LOW
t_WHGL
ADV# LOW to WE# HIGH
t_VLWH
WE# HIGH to read valid
t_WHQV
WRITE Operation to Asynchronous Read Transition
WE# HIGH to address valid
t_WHAV
Write to Synchronous Read Specification
WE# HIGH to CLK HIGH @ 110 MHz
t_WHCH
WE# HIGH to CE# LOW
t_WHEL
WE# HIGH to ADV# LOW
t_WHVL
Write Specifications with Clock Active
ADV# HIGH to WE# LOW
t_VHWL
CLK HIGH to WE# LOW
t_CHWL
Min
150
0
40
40
40
0
0
0
20
200
0
0
200
0
55
t_{AVQV + 30}
15
9
7
–
–
Max
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
27
27
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3
10
4
5
3, 7
3, 7
3, 7
3, 7
8
3, 6, 9
ns
3, 6, 11
ns
3, 6, 11
ns
3, 6, 11
ns
11
ns
11
Notes:
1. Write timing characteristics during erase suspend are the same as WRITE-only opera-
tions.
2. A WRITE operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width LOW (^tWLWH or ^tELEH) is defined from CE# or WE# LOW (whichever
occurs last) to CE# or WE# HIGH (whichever occurs first). Hence, ^tWLWH = ^tELEH = ^tWLEH
= ^tELWH.
5. Write pulse width HIGH (^tWHWL or ^tEHEL) is defined from CE# or WE# HIGH (whichever
occurs first) to CE# or WE# LOW (whichever occurs last). Hence, ^tWHWL = ^tEHEL = ^tWHEL
= ^tEHW.
6. ^tWHCH must be met when transitioning from a WRITE cycle to a synchronous burst read.
In addition CE# or ADV# must toggle when WE# goes HIGH.
7. V_PP and WP# must be at a valid level until erase or program success is determined.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
73
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