EP1S30F780C7 Datasheet, PDF (544/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Software Support
Figure 5–45. SERDES Bypass LVDS Receiver Using M512 RAM Block as the Deserializer
RXp
RXn
rx_inclk
DDIO In
datain[0]
dataout_h[0]
inclock
dataout_l[0]
inclock
RX_PLL
÷1 clock1
÷2 clock0
clock
q[4..0]
W-UpCounter
clock
q[2..0]
R-UpCounter
Simple Dual Port
RX_SESB
512 Bits
datain[1..0]
dataout[7..0]
waddr[7..0]
wclock
raddr[5..0]
rclock
waddr[7..5]
Core data
raddr[5..3]
Core clock
Figure 5–46. SERDES Bypass LVDS Transmitter Using M512 RAM Block as Deserializer
core_data
core_clk
inclock
RX_PLL
÷1 clock1
×2 clock0
clock
q[2..0]
W-UpCounter
clock
q[5..0]
R-UpCounter
Simple Dual Port ×2×8
TX_SESB
512 Bits
datain[7..0]
dataout[7..0]
waddr[5..0]
wclock
raddr[7..0]
rclock
waddr[7..5]
DDIO Out
datain_h[0]
dataout_h[0]
datain_l[0]
dataout_l[0]
outclock
raddr[5..3]
V_CC
GND
RX_PLL
datain_h[0]
/1 clock1
datain_l[0]
/2 clock0
outclock
TXp
TXn
tx_outclk
5–72
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005