EP1S30F780C7 Datasheet, PDF (359/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

General-Purpose PLLs in Stratix & Stratix GX Devices
Figure 1–22. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
PLL5_OUT[3..0] CLK14 (1)
PLL5_FB CLK15(2)
CLK12 (1) _CLK13 (2)
Regional
Clocks
RCLK2
RCLK3
Global
Clocks
Regional
Clocks
RCLK6
RCLK7
E[0..3]
PLL 5
PLL 11
L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1
L0 L1 G0 G1 G2 G3 G0 G1 G2 G3 L0 L1
PLL 6
PLL 12
PLL11_OUT
RCLK10
RCLK11
G12
G13
G14
G15
G4
G5
G6
G7
RCLK12
RCLK13
PLL12_OUT
PLL6_OUT[3..0] PLL6_FB
CLK6 (1)
CLK4 (1) CLK5(2)
CLK7 (2)
Notes to Figures 1–22:
(1) CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL’s inclk0 port.
(2) CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL’s inclk1 port.
Altera Corporation
July 2005
1–49
Stratix Device Handbook, Volume 2