EP1S30F780C7 Datasheet, PDF (458/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

I/O Pad Placement Guidelines
I/O Pad
Placement
Guidelines
Differential termination for Stratix devices is supported for the left and
right I/O banks. Differential termination for Stratix GX devices is
supported for the left, source-synchronous I/O bank. Some of the clock
input pins are in the top and bottom I/O banks, which do not support
differential termination. Clock pins CLK[1,3,8,10] support differential
on-chip termination. Clock pins CLK[0,2,9,11], CLK[4-7], and CLK[12-15]
do not support differential on-chip termination.
Transceiver Termination
Stratix GX devices feature built-in on-chip termination within the
transceiver at both the transmit and receive buffers. This termination
improves signal integrity and provides support for the 1.5-V PCML I/O
standard.
This section provides pad placement guidelines for the programmable
I/O standards supported by Stratix and Stratix GX devices and includes
essential information for designing systems using the devices' selectable
I/O capabilities. These guidelines will reduce noise problems so that
FPGA devices can maintain an acceptable noise level on the line from the
V_CCIO supply. Since Altera FPGAs require that a separate V_CCIO power
each bank, these noise issues do not have any effect when crossing bank
boundaries and these guidelines do not apply. Although pad placement
rules need not be considered between I/O banks, some rules must be
considered if you are using a VREF signal in a PLLOUT bank. Note that the
signals in the PLLOUT banks share the V_REF supply with neighboring I/O
banks and, therefore, must adhere to the V_REF rules discussed in “VREF
Pad Placement Guidelines”.
Differential Pad Placement Guidelines
To avoid cross coupling and maintain an acceptable noise level on the
V_CCIO supply, there are restrictions on the placement of single-ended I/O
pads in relation to differential pads. Use the following guidelines for
placing single-ended pads with respect to differential pads in Stratix
devices. These guidelines apply for LVDS, HyperTransport technology,
LVPECL, and PCML I/O standards. The differential pad placement
guidelines do not apply for differential HSTL and differential SSTL
output clocks since each differential output clock is essentially
implemented using two single-ended output buffers. These rules do not
apply to differential HSTL input clocks either even though the dedicated
input buffers are used. However, both differential HSTL and differential
SSTL output standards must adhere to the single-ended (VREF) pad
placement restrictions discussed in “VREF Pad Placement Guidelines”.
4–30
Stratix Device Handbook, Volume 2
Altera Corporation
June 2006