EP1S30F780C7 Datasheet, PDF (484/864 Pages) Altera Corporation – Stratix Device Handbook, Volume 1

Principles of SERDES Operation
Figure 5–7. Stratix Programmable Transmitter Clock
Stratix
Logic Array
Transmitter Circuit
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Parallel
Register
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Serial
Register
×W
Fast
PLL
TXLOADEN
TXOUT+
TXOUT−
SDR Transmitter Clock Output
You can route the high-frequency clock internally generated by the PLL
out as a transmitter clock output on any of the differential channels. The
high-frequency clock output allows Stratix devices to support
applications that require a 1-to-1 relationship between the clock and data.
The path of the high-speed clock is shown in Figure 5–8. A programmable
inverter allows you to drive the signal out on either the negative edge of
the clock or 180º out of phase with the streaming data.
5–12
Stratix Device Handbook, Volume 2
Altera Corporation
July 2005