EP3C120F484C7N Datasheet, PDF (28/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet

1–28
Chapter 1: Cyclone III Device Datasheet
Glossary
Table 1–39. Glossary (Part 2 of 5)
Letter
Term
Definitions
N
—
—
O
—
—
The following block diagram highlights the PLL Specification parameters.
P PLL Block
CLK
Core Clock
Switchover
CLKOUT Pins
f_{OUT _EXT}
fIN
fINPFD
N
PFD
CP
LF
VCO fVCO
Counters ^fOUT
C0..C4
GCLK
Q
—
R_L
Receiver Input
R ^Waveform
Phase tap
M
Key
Reconfigurable in User Mode
—
Receiver differential input discrete resistor (external to Cyclone III devices).
Receiver Input Waveform for LVDS and LVPECL Differential Standards.
Single-Ended Waveform
V_ID
V_CM
Positive Channel (p) = V_IH
Negative Channel (n) = V_IL
Ground
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V_ID
0V
V_ID
p-n
RSKM (Receiver
input skew
margin)
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation