EP3C120F484C7N Datasheet, PDF (23/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet

Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
1–23
Table 1–32 lists the FPGA sampling window specifications for Cyclone III devices.
Table 1–32. Cyclone III Devices FPGA Sampling Window (SW) Requirement – Read Side ⁽¹⁾
Memory Standard
Column I/Os
Setup
Hold
Row I/Os
Setup
Hold
Wraparound Mode
Setup
Hold
C6
DDR2 SDRAM
580
550
690
640
850
800
DDR SDRAM
585
535
700
650
870
820
QDRII SRAM
785
735
805
755
905
855
C7
DDR2 SDRAM
705
650
770
715
985
930
DDR SDRAM
675
620
795
740
970
915
QDRII SRAM
900
845
910
855
1085
1030
C8
DDR2 SDRAM
785
720
930
870
1115
1055
DDR SDRAM
800
740
915
855
1185
1125
QDRII SRAM
1050
990
1065
1005
1210
1150
I7
DDR2 SDRAM
765
710
855
800
1040
985
DDR SDRAM
745
690
880
825
1000
945
QDRII SRAM
945
890
955
900
1130
1075
A7
DDR2 SDRAM
805
745
1020
960
1145
1085
DDR SDRAM
880
820
955
935
1220
1160
QDRII SRAM
1090
1030
1105
1045
1250
1190
Note to Table 1–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Table 1–33 lists the transmitter channel-to-channel skew specifications for Cyclone III
devices.
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side ⁽¹⁾
Memory
Standard
I/O Standard
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
Column I/Os (ps)
Lead
Lag
C6
790
380
870
490
750
320
860
350
780
410
830
510
C7
Row I/Os (ps)
Lead
Lag
790
380
870
490
750
320
860
350
780
410
830
510
(Part 1 of 2)
Wraparound Mode (ps)
Lead
Lag
890
480
970
590
850
420
960
450
880
510
930
610
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2