EP3C120F484C7N Datasheet, PDF (10/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet

1–10
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III devices support Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG,
nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate.
Table 1–12 lists the hysteresis specifications across supported V_CCIO range for Schmitt
trigger inputs in Cyclone III devices.
Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices
Symbol
Parameter
V_SCHMITT
Hysteresis for Schmitt trigger
input
Conditions
V_CCIO = 3.3 V
V_CCIO = 2.5 V
V_CCIO = 1.8 V
V_CCIO = 1.5 V
Minimum
200
200
140
110
Typical
—
—
—
—
Maximum Unit
—
mV
—
mV
—
mV
—
mV
I/O Standard Specifications
The following tables list input voltage sensitivities (V_IH and V_IL), output voltage (V_OH
and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O standards
supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O
standard specifications for Cyclone III devices.
Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications ^{(1), (2)}
I/O Standard
V_CCIO (V)
Min Typ Max
V_IL (V)
Min Max
V_IH (V)
Min
Max
V_OL (V)
Max
V_OH (V)
Min
I_OL
I_OH
(mA) (mA)
3.3-V LVTTL ⁽³⁾ 3.135 3.3 3.465 — 0.8
1.7
3.6
0.45
2.4
4
–4
3.3-V LVCMOS ⁽³⁾ 3.135 3.3 3.465 — 0.8
3.0-V LVTTL ⁽³⁾
2.85 3.0 3.15 –0.3 0.8
3.0-V LVCMOS ⁽³⁾ 2.85 3.0 3.15 –0.3 0.8
2.5-V LVTTL and
LVCMOS ⁽³⁾
2.375 2.5
2.625 –0.3
0.7
1.7
3.6
0.2
1.7 V_CCIO + 0.3 0.45
1.7 V_CCIO + 0.3
0.2
1.7
3.6
0.4
V_CCIO – 0.2 2
–2
2.4
4
–4
V_CCIO – 0.2 0.1 –0.1
2.0
1
–1
1.8-V LVTTL and
LVCMOS
1.71 1.8
1.89
–0.3
0.35 *
V_CCIO
0.65 *
V_CCIO
2.25
0.45
V_CCIO –
0.45
2
–2
1.5-V LVCMOS
1.425 1.5
1.575
–0.3
0.35 *
V_CCIO
0.65 *
V_CCIO
V_CCIO + 0.3
0.25 *
V_CCIO
0.75 *
V_CCIO
2
–2
1.2-V LVCMOS
1.14
1.2
1.26
–0.3
0.35 *
V_CCIO
0.65 *
V_CCIO
V_CCIO + 0.3
0.25 *
V_CCIO
0.75 *
V_CCIO
2
–2
3.0-V PCI
2.85
3.0
3.15
—
0.3 *
V_CCIO
0.5 *
V_CCIO
V_CCIO + 0.3 0.1 * V_CCIO 0.9 * V_CCIO
1.5
–0.5
3.0-V PCI-X
2.85
3.0
3.15
—
0.35*
V_CCIO
0.5 *
V_CCIO
V_CCIO + 0.3 0.1 * V_CCIO 0.9 * V_CCIO
1.5
–0.5
Notes to Table 1–13:
(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13, refer to “Single-ended Voltage referenced I/O Standard”
in “Glossary” on page 1–27.
(2) AC load CL = 10 pF.
(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III
Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation