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EP3C120F484C7N Datasheet, PDF (17/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet | |||
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Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
1â17
Table 1â24 lists the active configuration mode specifications for Cyclone III devices.
Table 1â24. Cyclone III Devices Active Configuration Mode Specifications
Programming Mode
DCLK Range
Unit
Active Parallel (AP)
Active Serial (AS)
20 â 40
MHz
20 â 40
MHz
Table 1â25 lists the JTAG timing parameters and values for Cyclone III devices.
Table 1â25. Cyclone III Devices JTAG Timing Parameters (1)
Symbol
Parameter
Min Max Unit
tJCP
TCK clock period
40 â ns
tJCH
TCK clock high time
20 â ns
tJCL
TCK clock low time
20 â ns
tJPSU_TDI JTAG port setup time for TDI
1
â
ns
tJPSU_TMS JTAG port setup time for TMS
3
â
ns
tJPH
JTAG port hold time
10 â ns
tJPCO
JTAG port clock to output (2)
tJPZX
JTAG port high impedance to valid output (2)
â 15 ns
â 15 ns
tJPXZ
JTAG port valid output to high impedance (2)
â 15 ns
tJSSU
Capture register setup time
5
â ns
tJSH
Capture register hold time
10 â ns
tJSCO
Update register clock to output
â 25 ns
tJSZX
Update register high impedance to valid output
â 25 ns
tJSXZ
Update register valid output to high impedance
â 25 ns
Notes to Table 1â25:
(1) For more information about JTAG waveforms, refer to âJTAG Waveformâ in âGlossaryâ on page 1â27.
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several system interfacing, for example, the high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using
the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds with typical DDR SDRAM memory interface setup. I/O using
general-purpose I/O standards such as 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are
capable of a typical 200 MHz interfacing frequency with a 10 pF load.
1 Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
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