|
EP3C120F484C7N Datasheet, PDF (22/34 Pages) Altera Corporation – 1. Cyclone III Device Datasheet | |||
|
◁ |
1â22
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1â30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min Max Min Max Min Max
Output jitter
(peak to peak)
â
â 500 â 500 â 550 ps
tLOCK (2)
â
â
1
â
1
â
1
ms
Notes to Table 1â30:
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1â31. Cyclone III Devices LVDS Receiver Timing Specifications (1)
Symbol
Modes
C6
Min Max
C7, I7
Min Max
C8, A7
Min Max
Ã10
5 437.5 5
370
5
320
Ã8
5 437.5 5
370
5
320
fHSCLK (input
Ã7
clock frequency)
Ã4
5 437.5 5
370
5
320
5 437.5 5
370
5
320
Ã2
5 437.5 5
370
5
320
Ã1
5 437.5 5 402.5 5 402.5
Ã10
100 875 100 740 100 640
Ã8
80 875 80 740 80 640
HSIODR
Ã7
70 875 70 740 70 640
Ã4
40 875 40 740 40 640
Ã2
20 875 20 740 20 640
Ã1
10 437.5 10 402.5 10 402.5
SW
â
â 400 â 400 â 400
Input jitter
tolerance
â
â 500 â 500 â 550
tLOCK (2)
â
â
1
â
1
â
1
Notes to Table 1â31:
(1) LVDS receiver is supported at all banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
ps
ms
External Memory Interface Specifications
Cyclone III devices support external memory interfaces up to 200 MHz. The external
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
|
▷ |