ER3105DI Datasheet, PDF (23/25 Pages) Altera Corporation – 500mA Wide VIN Synchronous Buck Regulator

Page 23
capacitors have significant derating on voltage and temperature, depending on the type. Please refer to the ceramic capacitor
datasheet for more details.
60
45
30
15
0
-15
-30
100
1k
10k
100k
1M
FREQUENCY (Hz)
180
150
120
90
60
30
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 62. SIMULATED LOOP GAIN
Layout Considerations
Proper layout of the power converter will minimize EMI and noise and insure first pass success of the design. PCB layouts are
available from Altera. In addition, Figure 63 will make clear the important points in PCB layout. In reality, PCB layout of the
ER3105DI is quite simple.
A multi-layer printed circuit board with GND plane is recommended. Figure 63 shows the connections of the critical components
in the converter. Note that capacitors C_IN and C_OUT could each represent multiple physical capacitors. The most critical
connections are to tie the PGND pin to the package GND pad and then use vias to directly connect the GND pad to the system
GND plane. This connection of the GND pad to system plane insures a low impedance path for all return current, as well as an
excellent thermal path to dissipate heat. With this connection made, place the high frequency MLCC input capacitor near the PVIN
pin and use vias directly at the capacitor pad to tie the capacitor to the system GND plane.
The boot capacitor is easily placed on the PCB side opposite the controller IC and 2 vias directly connect the capacitor to BOOT
and SW.
Place a 1µF MLCC near the AVINO pin and directly connect its return with a via to the system GND plane.
Place the feedback divider close to the FB pin and do not route any feedback components near SW or BOOT. If external
components are used for SS, COMP or FSW the same advice applies.
March 2014 Altera Corporation
09616
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A