ER3105DI Datasheet, PDF(22/25 Page) Altera Corporation – 500mA Wide VIN Synchronous Buck Regulator

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ER3105DI Datasheet, PDF (22/25 Pages) Altera Corporation – 500mA Wide VIN Synchronous Buck Regulator

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Page 22

ï·cz1 = -R----6--1-C-----6- , ï·cz2 = R-----2--1-C-----3-ï¬ ï·cp1= -R-C---6-6--C---+--6--C-C----7-7-ï¬ ï·cp2= -C-R---3-2--R---+--2--R-R----3-3-

Choose Loop bandwidth fc less than 100kHz

Gain margin: >10dB

Phase margin: >40Â°

The compensator design procedure is as follows:

The loop gain at crossover frequency of fc has a unity gain. Therefore, the compensator resistance R6 is determined by Equation 9.

R6 = 2----ï°-G---f--Mc---V---ï-o--V--C--F--o--B--R----t = 27.3ï´103 ï fcVoCo

(EQ. 9)

Where GM is the trans-conductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then given by

Equation 10.

C6 = R----R-o---C-6----o- = -V-I--o-o--R-C----6-o- ,C7= max(R----R-c---C-6----o-,-ï°---f--S----1W-----R-----6-)

(EQ. 10)

Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero

frequency or half switching frequency, whichever is lower in Equation 10. An optional zero can boost the phase margin. ï·CZ2 is a

zero due to R2 and C3ï®

Put compensator zero 2 to 5 times fc

C3= -ï°---f--c-1--R-----2-

(EQ. 11)

Example: VIN = 12V, VO = 5V, IO = 500mA, fSW = 500kHz, R2 = 90.9kï, Co = 22ÂµF/5mâ¦, L = 39ÂµH, fc = 50kHz, then

compensator resistance R6:

R6 = 27.3ï´103 ï 50kHz ï 5V ï 22ïF = 150.2kï

(EQ. 12)

It is acceptable to use 150kïï as theï closest standard value for R6.

C6 = -5---0---0--5--m-V----A--ï---2-ï--2-1---ï5----0F---k----ï---= 1.46nF

(EQ. 13)

C7= max(5----m----1--ï-5---0--ï--k-2---ï2----ï----F--,ï°-----ï---5----0---0----k---H---1--z-----ï---1---5---0----k----ï---)= (0.7pF,4.2pF) (EQ. 14)

It is also acceptable to use the closest standard values for C6 and C7. There is approximately 3pF parasitic capacitance from VCOMP to

GND; Therefore, C7 is optional. Use C6 = 1500pF and C7 = OPEN.

C3= ï°-----ï---5----0---k----H-----z1----ï---9----0---.--9---k----ï--- = 70pF

(EQ. 15)

Use C3 = 68pF. Note that C3 may increase the loop bandwidth from previous estimated value. Figure 62 shows the simulated

voltage loop gain. It is shown that it has a 75kHz loop bandwidth with a 61Â° phase margin and 6dB gain margin. It may be more

desirable to achieve an increased gain margin. This can be accomplished by lowering R6 by 20% to 30%. In practice, ceramic

ER3105DI 500mA Wide VIN Synchronous Buck Regulator

09616

March 14, 2014

March 2014 Altera Corporation

Rev A

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