ER3105DI Datasheet, PDF (17/25 Pages) Altera Corporation – 500mA Wide VIN Synchronous Buck Regulator

Page 17
Power-OK
POK is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage via the FB pin.
POK is actively held low when EN is low and during the buck regulator soft-start period. After the soft-start period completes,
POK becomes high impedance provided the FB pin is within the range specified in the “Electrical Specifications” on page 3.
Should FB exit the specified window, POK will be pulled low until FB returns. Over-temperature faults also force POK low until
the fault condition is cleared by an attempt to soft-start. There is an internal 5M internal pull-up resistor.
PWM Control Scheme
The ER3105DI employs peak current-mode pulse-width modulation (PWM) control for fast transient response and pulse-by-pulse
current limiting, as shown in the “Functional Block Diagram” on page 16. The current loop consists of the current sensing circuit,
slope compensation ramp, PWM comparator, oscillator and latch. Current sense trans-resistance is typically 600mV/A and slope
compensation rate, Se, is typically 450mV/T where T is the switching cycle period. The control reference for the current loop
comes from the error amplifier’s output (V_COMP).
A PWM cycle begins when a clock pulse sets the PWM latch and the upper FET is turned on. Current begins to ramp up in the upper
FET and inductor. This current is sensed (V_CSA), converted to a voltage and summed with the slope compensation signal. This
combined signal is compared to V_COMP and when the signal is equal to V_COMP, the latch is reset. Upon latch reset the upper FET is
turned off and the lower FET turned on allowing current to ramp down in the inductor. The lower FET will remain on until the clock
initiates another PWM cycle. Figure 56 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate
the sum of the current sense and slope compensation signal.
Output voltage is regulated as the error amplifier varies V_COMP and thus output inductor current. The error amplifier is a
trans-conductance type and its output (COMP) is terminated with a series RC network to GND. This termination is internal
(150k/54pF) if the COMP pin is tied to AVINO. Additionally, the trans-conductance for COMP = AVINO is 50µs vs 220µs for
external RC connection. Its non-inverting input is internally connected to a 600mV reference voltage and its inverting input is
connected to the output voltage via the FB pin and its associated divider network.
V_COMP
V_CSA
DUTY
CYCLE
I_L
V_OUT
FIGURE 56. PWM OPERATION WAVEFORMS
Light Load Operation
At light loads, converter efficiency may be improved by enabling variable frequency operation (PFM). Connecting the SYNC pin
to GND will allow the controller to choose such operation automatically when the load current is low. Figure 57 shows the DCM
operation. The IC enters the DCM mode of operation when 8 consecutive cycles of inductor current crossing zero are detected.
This corresponds to a load current equal to 1/2 the peak-to-peak inductor ripple current and set by the following Equation 2:
I_OUT = ^V-----^O---₂-^U---_L-^T--_F--^--_S-¹---_W-–-----^D-----^
(EQ. 2)
where D = duty cycle, F_SW = switching frequency, L = inductor value, I_OUT = output loading current, V_OUT = output voltage.
While operating in PFM mode, the regulator controls the output voltage with a simple comparator and pulsed FET current. A
comparator signals the point at which FB is equal to the 600mV reference at which time the regulator begins providing pulses of
current until FB is moved above the 600mV reference by 1%. The current pulses are approximately 300mA and are issued at a
frequency equal to the converters programmed PWM operating frequency.
March 2014 Altera Corporation
09616
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A