EPC1441PC8 Datasheet, PDF (23/26 Pages) Altera Corporation – Configuration Devices for SRAM-Based LUT Devices

Pin Information
Page 23
Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 3 of 3)
Pin Name
Pin Number
8-Pin
PDIP ⁽¹⁾
20-Pin
PLCC
32-Pin
TQFP ⁽²⁾
Pin Type
TCK
N/A
3
32 Input
VCCSEL
N/A
5
3
Input
VPPSEL
N/A
14
17 Input
VPP
N/A
18
23 Power
VCC
7, 8
20
27 Power
GND
5
10
12 Ground
Notes to Table 20:
(1) This package is available for EPC1 and EPC1441 devices only.
(2) This package is available for EPC2 and EPC1441 devices only.
Description
JTAG clock pin. Connect this pin to GND if the JTAG
circuitry is not used.
This pin is only available in EPC2 devices.
Mode select for V_CC supply. VCCSEL must be connected to
GND if the device uses a 5.0-V power supply (V_CC = 5.0 V).
VCCSEL must be connected to V_CC if the device uses a
3.3-V power supply (V_CC = 3.3 V).
This pin is only available in EPC2 devices.
Mode select for V_PP. supply. VPPSEL must be connected to
GND if V_PP uses a 5.0-V power supply (V_PP = 5.0 V).
VPPSEL must be connected to V_CC if V_PP uses a 3.3-V
power supply (V_PP = 3.3 V).
This pin is only available in EPC2 devices.
Programming power pin. For the EPC2 device, this pin is
normally tied to V_CC. If the V_CC of the EPC2 device is 3.3 V,
tie V_PP to 5.0 V to improve ISP time. For EPC1 and
EPC1441 devices, V_PP must be tied to V_CC.
This pin is only available in EPC2 devices.
Power pin.
Ground pin. Place a 0.2-µF decoupling capacitor between
the VCC and GND pins.
January 2012 Altera Corporation
Configuration Devices for SRAM-Based LUT Devices