EPC1441PC8 Datasheet, PDF (18/26 Pages) Altera Corporation – Configuration Devices for SRAM-Based LUT Devices

Page 18
Timing Information
Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max Units
t_OEW
OE low pulse width (reset) to guarantee counter reset
100
—
—
ns
t_OEC
OE low (reset) to DCLK disable delay
—
—
20
ns
t_NRCAS
OE low (reset) to nCASC delay
—
—
25
ns
Note to Table 10:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Table 11 lists the timing parameters when using EPC1, EPC1064, EPC1064V, EPC1213,
and EPC1441 devices when configuring the FLEX 8000 device.
Table 11. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441
Devices
Symbol
Parameter
t_{O EZX}
t_CSZX
t_CSXZ
t_CSS
t_CSH
t_{D SU}
t_{D H}
t_CO
t_CK
f_CK
t_CL
t_CH
t_XZ
t_{O EW}
t_CASC
t_CKXZ
t_{C EO UT}
OE high to DATA output enabled
nCS low to DATA output enabled
nCS high to DATA output disabled
nCS low setup time to first DCLK rising edge
nCS low hold time after DCLK rising edge
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK to DATA out delay
Clock period
Clock frequency
DCLK low time
DCLK high time
OE low or nCS high to DATA output disabled
OE pulse width to guarantee counter reset
Last DCLK + 1 to nCASC low delay
Last DCLK + 1 to DATA tri-state delay
nCS high to nCASC high delay
EPC1064V
EPC1064 and
EPC1213
EPC1 and
EPC1441
Unit
Min Max Min Max Min Max
— 75 — 50 — 50 ns
— 75 — 50 — 50 ns
— 75 — 50 — 50 ns
150 — 100 — 50 — ns
0
—
0
—
0
— ns
75 — 50 — 50 — ns
0
—
0
—
0
— ns
— 100 — 75 — 75 ns
240 — 160 — 100 — ns
—
4
—
6
—
8 MHz
120 — 80 — 50 — ns
120 — 80 — 50 — ns
— 75 — 50 — 50 ns
150 — 100 — 100 — ns
— 90 — 60 — 50 ns
— 75 — 50 — 50 ns
— 150 — 100 — 100 ns
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation