EPC1441PC8 Datasheet, PDF (16/26 Pages) Altera Corporation – Configuration Devices for SRAM-Based LUT Devices

Page 16
Timing Information
Timing Information
Figure 5 shows the timing waveform when using a configuration device.
Figure 5. Timing Waveform Using a Configuration Device
nINIT_CONF or VCC/nCONFIG
t_POR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA
t_OEZX
User I/O
INIT_DONE
t_DSU t_CL
D₀ D₁
t_CO
Tri-State
t_CH
t_DH
D₂ D₃
D_n
Tri-State
(1)
User Mode
Note to Figure 5:
(1) The EPC2 device drives DCLK low and DATA high after configuration. The EPC1 and EPC1441 devices drive DCLK low and tri-state DATA after
configuration.
Table 8 lists the timing parameters when using EPC2 devices at 3.3 V.
Table 8. Timing Parameters when Using EPC2 devices at 3.3 V
Symbol
Parameter
Min
Typ
Max Units
t_{PO R}
POR delay ⁽¹⁾
—
—
200
ms
t_OEZX
OE high to DATA output enabled
—
—
80
ns
t_CE
OE high to first rising edge on DCLK
—
—
300
ns
t_DSU
Data setup time before rising edge on DCLK
30
—
—
ns
t_DH
Data hold time after rising edge on DCLK
0
—
—
ns
t_CO
DCLK to DATA out
—
—
30
ns
t_{CD OE}
DCLK to DATA enable/disable
—
—
30
ns
f_CLK
DCLK frequency
5
7.7
12.5 MHz
t_MCH
DCLK high time for the first device in the configuration chain
40
65
100
ns
t_MCL
DCLK low time for the first device in the configuration chain
40
65
100
ns
t_SCH
DCLK high time for subsequent devices
40
—
—
ns
t_SCL
DCLK low time for subsequent devices
40
—
—
ns
t_CASC
DCLK rising edge to nCASC
—
—
25
ns
t_CCA
nCS to nCASC cascade delay
—
—
15
ns
t_OEW
OE low pulse width (reset) to guarantee counter reset
100
—
—
ns
t_OEC
OE low (reset) to DCLK disable delay
—
—
30
ns
t_NRCAS
OE low (reset) to nCASC delay
—
—
30
ns
Note to Table 8:
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Configuration Devices for SRAM-Based LUT Devices
January 2012 Altera Corporation