EPC1441PC8 Datasheet, PDF (15/26 Pages) Altera Corporation – Configuration Devices for SRAM-Based LUT Devices

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
Page 15
Figure 4 shows the timing requirements for the JTAG signals.
Figure 4. EPC2 Device JTAG Waveforms
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t_JCH
t_JCP
t_JCL
t_JPSU
t_JPZX
t_JSSU
t_JSZX
t_JPCO
t_JSH
t_JSCO
t_JPH
t_JPXZ
t_JSXZ
Table 7 lists the timing parameters and values for configuration devices.
Table 7. JTAG Timing Parameters and Values
Symbol
Parameter
Min
Max
Unit
t_JCP
TCK clock period
100
—
ns
t_JCH
TCK clock high time
50
—
ns
t_JCL
TCK clock low time
50
—
ns
t_JPSU
JTAG port setup time
20
—
ns
t_JPH
JTAG port hold time
45
—
ns
t_JPCO
JTAG port clock to output
—
25
ns
t_JPZX
JTAG port high impedance to valid output
—
25
ns
t_JPXZ
JTAG port valid output to high impedance
—
25
ns
t_JSSU
Capture register setup time
20
—
ns
t_JSH
Capture register hold time
45
—
ns
t_JSCO
Update register clock to output
—
25
ns
t_JSZX
Update register high impedance to valid output
—
25
ns
t_JSXZ
Update register valid output to high impedance
—
25
ns
January 2012 Altera Corporation
Configuration Devices for SRAM-Based LUT Devices