EPC1441PC8 Datasheet, PDF (11/26 Pages) Altera Corporation – Configuration Devices for SRAM-Based LUT Devices

Power and Operation
Page 11
Table 3 lists the relationship between the V_CC and V_PP voltage levels and the required
logic level for VCCSEL and VPPSEL pins. A high logic level means the pin should be
connected to V_CC, while a low logic level means the pin should be connected to GND.
Table 3. VCCSEL and VPPSEL Pin Functions on the EPC2 Device
VCC Voltage Level
(V)
3.3
3.3
5.0
VPP Voltage Level
(V)
3.3
5.0
5.0
VCCSEL Pin Logic
Level
High
High
Low
VPPSEL Pin Logic
Level
High
Low
Low
At a 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except for DATA, DCLK, and
nCASC pins. The DATA and DCLK pins are used only to interface between the EPC2
device and the FPGA it is configuring. Table 4 lists the voltage tolerences of all EPC2
device pins.
Table 4. EPC2 Device Input and Bidirectional Pin Voltage Tolerance
Pin
DATA
DCLK
nCASC
OE
nCS
VCCSEL
VPPSEL
nINIT_CONF
TDI
TMS
TCK
5.0-V Operation
5.0-V Tolerant
v
v
v
v
v
v
v
v
v
v
v
3.3-V Tolerant
v
v
v
v
v
v
v
v
v
v
v
3.3-V Operation
5.0-V Tolerant
—
—
—
v
v
v
v
v
v
v
v
3.3-V Tolerant
v
v
v
v
v
v
v
v
v
v
v
If one EPC1, EPC2, or EPC1441 configuration device is powered at 3.3 V, the nSTATUS
and CONF_DONE pull-up resistors must be connected to 3.3 V. If these configuration
devices are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors can be
connected to either 3.3 V or 5.0 V.
January 2012 Altera Corporation
Configuration Devices for SRAM-Based LUT Devices