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EP2C5F256I8N Datasheet, PDF (153/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet | |||
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DC Characteristics and Timing Specifications
Table 5â51. LVDS Receiver Timing Specification
â6 Speed Grade
â7 Speed Grade
â8 Speed Grade
Symbol Conditions
Unit
Min Typ Max Min Typ Max Min Typ Max
fH S C L K
Ã10
(input clock
Ã8
frequency)
Ã7
10 â 402.5 10 â
320
10 â 320 (1) MHz
10 â 402.5 10 â
320
10 â 320 (1) MHz
10 â 402.5 10 â
320
10 â 320 (1) MHz
Ã4
10 â 402.5 10 â
320
10 â 320 (1) MHz
Ã2
10 â 402.5 10 â
320
10 â 320 (1) MHz
Ã1
10 â 402.5 10 â 402.5 10 â 402.5 (3) MHz
HSIODR
Ã10
100 â
805 100 â
640 100 â 640 (2) Mbps
Ã8
80 â
805
80 â
640
80 â 640 (2) Mbps
Ã7
70 â
805
70 â
640
70 â 640 (2) Mbps
Ã4
40 â
805
40 â
640
40 â 640 (2) Mbps
Ã2
20 â
805
20 â
640
20 â 640 (2) Mbps
Ã1
10 â 402.5 10 â 402.5 10 â 402.5 (4) Mbps
SW
â
ââ
300
ââ
400
ââ
400
ps
Input jitter
tolerance
â
ââ
500
ââ
500
ââ
550
ps
tL O C K
â
ââ
100
ââ
100
â â 100 (5) ps
Notes to Table 5â51:
(1) For extended temperature devices, the maximum input clock frequency for x10 through x2 modes is 275 MHz.
(2) For extended temperature devices, the maximum data rate for x10 through x2 modes is 550 Mbps.
(3) For extended temperature devices, the maximum input clock frequency for x1 mode is 340 MHz.
(4) For extended temperature devices, the maximum data rate for x1 mode is 340 Mbps.
(5) For extended temperature devices, the maximum lock time is 500 us.
External Memory Interface Specifications
Table 5â52 shows the DQS bus clock skew adder specifications.
Table 5â52. DQS Bus Clock Skew Adder Specifications
Mode
DQS Clock Skew Adder
Unit
Ã9
155
ps
Ã18
190
ps
Note to Table 5â52:
(1) This skew specification is the absolute maximum and minimum skew. For
example, skew on a Ã9 DQ group is 155 ps or ±77.5 ps.
Altera Corporation
February 2008
5â63
Cyclone II Device Handbook, Volume 1
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