EP2C5F256I8N Datasheet, PDF (138/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Timing Specifications
Table 5–44. Maximum Input Clock Toggle Rate on Cyclone II Devices (Part 2 of 2)
Maximum Input Clock Toggle Rate on Cyclone II Devices (MHz)
I/O Standard
DIFFERENTIAL_SSTL_18_
CLASS_I
DIFFERENTIAL_SSTL_18_
CLASS_II
1.8V_DIFFERENTIAL_HSTL_
CLASS_I
1.8V_DIFFERENTIAL_HSTL_
CLASS_II
1.5V_DIFFERENTIAL_HSTL_
CLASS_I
1.5V_DIFFERENTIAL_HSTL_
CLASS_II
LVPECL
LVDS
1.2V_HSTL
1.2V_DIFFERENTIAL_HSTL
Column I/O Pins
Row I/O Pins
Dedicated Clock
Inputs
–6 –7 –8 –6 –7 –8 –6 –7 –8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
500 500 500 500 500 500 500 500 500
—
—
—
—
—
— 402 402 402
402 402 402 402 402 402 402 402 402
110 90
80
—
—
— 110 90
80
110 90
80
—
—
— 110 90
80
Table 5–45. Maximum Output Clock Toggle Rate on Cyclone II Devices (Part 1 of 4)
Maximum Output Clock Toggle Rate on Cyclone II Devices (MHz)
I/O Standard
LVTTL
Drive
Strength
Column I/O Pins (1) Row I/O Pins (1)
Dedicated Clock
Outputs
–6 –7 –8 –6 –7 –8 –6 –7 –8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
120 100 80 120 100 80 120 100 80
200 170 140 200 170 140 200 170 140
280 230 190 280 230 190 280 230 190
290 240 200 290 240 200 290 240 200
330 280 230 330 280 230 330 280 230
360 300 250 360 300 250 360 300 250
5–48
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008