EP2C5F256I8N Datasheet, PDF (119/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

DC Characteristics and Timing Specifications
EP2C70 Clock Timing Parameters
Tables 5–33 and 5–34 show the clock timing parameters for EP2C70
devices.
Table 5–33. EP2C70 Column Pins Global Clock Timing Parameters
Parameter
t_{C I N}
t_{C O U T}
t_{P L L C I N}
t_{P L L C O U T}
Fast Corner
Industrial Commercial
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Unit
1.575
1.651
2.914
3.105
3.174
ns
1.589
1.666
2.948
3.137
3.203
ns
–0.149
–0.158
0.27
0.268
0.089
ns
–0.135
–0.143
0.304
0.3
0.118
ns
Table 5–34. EP2C70 Row Pins Global Clock Timing Parameters
Parameter
t_{C I N}
t_{C O U T}
t_{P L L C I N}
t_{P L L C O U T}
Fast Corner
Industrial
1.463
1.465
–0.261
–0.259
Commercial
1.533
1.535
–0.276
–0.274
–6 Speed
Grade
2.753
2.769
0.109
0.125
–7 Speed
Grade
2.927
2.940
0.09
0.103
–8 Speed
Grade
Unit
3.010
ns
3.018
ns
–0.075
ns
–0.067
ns
Clock Network Skew Adders
Table 5–35 shows the clock network specifications.
Table 5–35. Clock Network Specifications
Name
Clock skew adder
EP2C5/A, EP2C8/A (1)
Clock skew adder
EP2C15A, EP2C20/A,
EP2C35, EP2C50,
EP2C70 (1)
Description
Max Unit
Inter-clock network, same bank
±88 ps
Inter-clock network, same side and ±88 ps
entire chip
Inter-clock network, same bank
±118 ps
Inter-clock network, same side and ±138 ps
entire chip
Note to Table 5–35:
(1) This is in addition to intra-clock network skew, which is modeled in the
Quartus II software.
Altera Corporation
February 2008
5–29
Cyclone II Device Handbook, Volume 1