EP2C5F256I8N Datasheet, PDF (150/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Timing Specifications
Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 2 of 2)
Symbol Conditions
Device
×10
operation
×8
in Mbps
×7
×4
×2
×1
t_{D U T Y}
—
TCCS
—
Output
—
jitter (peak
to peak)
t_{R I S E}
20–80%
t_{F A L L}
80–20%
t_{L O C K}
–6 Speed Grade
Min Typ Max
100 — 311
80 — 311
70 — 311
40 — 311
20 — 311
10 — 311
45 — 55
— — 200
— — 500
— — 500
— — 500
— — 100
–7 Speed Grade
Min Typ Max
100 — 311
80
— 311
70
— 311
40
— 311
20
— 311
10
— 311
45
—
55
—
—
200
—
— 500
—
— 500
—
— 500
—
— 100
–8 Speed Grade
Min Typ Max
100 — 311
80
— 311
70
— 311
40
— 311
20
— 311
10
— 311
45
—
55
—
— 200
—
— 500
Unit
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
—
— 500 ps
—
— 500 ps
—
— 100 μs
In order to determine the transmitter timing requirements, mini-LVDS
receiver timing requirements on the other end of the link must be taken
into consideration. The mini-LVDS receiver timing parameters are
typically defined as t_SU and t_H requirements. Therefore, the transmitter
timing parameter specifications are t_CO (minimum) and t_CO (maximum).
Refer to Figure 5–4 for the timing budget.
The AC timing requirements for mini-LVDS are shown in Figure 5–6.
Figure 5–6. mini-LVDS Transmitter AC Timing Specification
LVDSCLK[]n
LVDSCLK[]p
LVDS[]p
LVDS[]n
Notes to Figure 5–6:
(1) The data setup time, t_SU, is 0.225 × TUI.
(2) The data hold time, t_H, is 0.225 × TUI.
TUI
t_SU (1)
t_H (2)
t_SU (1)
t_H (2)
5–60
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008