EP53A8LQA Datasheet, PDF (15/21 Pages) Altera Corporation – Integrated Inductor

logic high and logic low is indeterminate.
EP53A8LQA External Voltage Divider
The external divider option is chosen by
connecting VID pins VS2-VS0 to V_IN or a logic
“1” or “high”. The EP53A8LQA uses a
separate feedback pin, V_FB, when using the
external divider. V_SENSE must be connected to
V_OUT as indicated in Figure 8.
The output voltage is selected by the following
formula:
( ) V_OUT
= 0.6V
1+
Ra
Rb
V_IN
4.7µF
0603
X7R
100Ω
EP53A8LQA
PVIN
VOUT
AVIN
VS0
VS1
VS2
ENABLE
PGND
VSENSE
VFB
AGND
V_OUT
R_A
10µF
0805
X7R
R_B
EP53A8LQA/EP53A8HQA
changed while the device is enabled.
Table 2 shows the VS0-VS2 pin logic states for
the EP53A8HQA and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
Table 2: EP53A8HQA VID Voltage Select Settings
VS2
VS1
VS0
VOUT
0
0
0
3.3
0
0
1
3.0
0
1
0
2.9
0
1
1
2.6
1
0
0
2.5
1
0
1
2.2
1
1
0
2.1
1
1
1
1.8
Figure 8. EP53A8LQA External VOUT Setting
R_a must be chosen as 237KΩ to maintain loop
gain. Then R_b is given as:
R = 142.2x103 Ω
b _{VOUT − 0.6}
V_OUT can be programmed over the range of
0.6V to (V_IN – 0.5V).
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
EP53A8HQA High VID Range
Programming
The EP53A8HQA V_OUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP53A8HQA does not have an
external divider option. As with the
EP53A8LQA, the VID pin settings can be
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Pre-Bias Start-up
The EP53A8xQA supports startup into a pre-
biased output of up to 1.5V. The output of the
EP53A8xQA can be pre-biased with a voltage
up to 1.5V when it is first enabled.
Input Filter Capacitor
The input filter capacitor requirement is a
4.7µF 0603 low ESR MLCC capacitor. The
input capacitor must use X7R or equivalent
dielectric formulation. Y5V or equivalent
dielectric formulations lose capacitance with
frequency, bias, and with temperature, and are
not suitable for switch-mode DC-DC converter
10366
July 21, 2015
www.altera.com/enpirion, Page 15
Rev D