EP53A8LQA Datasheet, PDF (14/21 Pages) Altera Corporation – Integrated Inductor

Application Information
V_IN
4.7µF
0603
X7R
EP53A8HQA
100Ω
PVIN
VOUT
AVIN
ENABLE
VS0
VS1
VS2
PGND
VSENSE
AGND
EP53A8LQA/EP53A8HQA
V_OUT
10µF
0805
X7R
The “High” VID set provides output voltage
settings ranging from 1.8V to 3.3V. This
version does not have an external divider
option. To specify this VID range, order part
number EP53A8HQA.
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
which in turn is connected to the non-inverting
input of the error amplifier. This allows the use
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage selected.
NOTE: The VID pins must not be left floating.
Figure 6. EP53A8HQA VID Application Circuit
V_IN
4.7µF
0603
X7R
EP53A8LQA
100Ω
PVIN
VOUT
AVIN
ENABLE
VS0
VS1
VS2
PGND
VSENSE
VFB
AGND
V_OUT
10µF
0805
X7R
Figure 7. EP53A8LQA VID Application Circuit
Output Voltage Programming
The EP53A8xQA utilizes a 3-pin VID to
program the output voltage value. The VID is
available in two sets of output VID
programming ranges. The VID pins should be
connected either to an external control signal,
AVIN or to AGND to avoid noise coupling into
the device.
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
also has an external divider option.
To specify this VID range, order part number
EP53A8LQA.
Table 1: EP53A8LQA VID Voltage Select Settings
VS2
VS1
VS0
VOUT
0
0
0
1.50
0
0
1
1.45
0
1
0
1.20
0
1
1
1.15
1
0
0
1.10
1
0
1
1.05
1
1
0
0.8
1
1
1
EXT
EP53A8L Low VID Range Programming
The EP53A8LQA is designed to provide a high
degree of flexibility in powering applications
that require low V_OUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
can be changed on the fly to implement glitch-
free voltage scaling.
Table 1 shows the VS2-VS0 pin logic states for
the EP53A8LQA and the associated output
voltage levels. A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
10366
July 21, 2015
www.altera.com/enpirion, Page 14
Rev D