AK4643 Datasheet, PDF (99/104 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/RCV/SPK-AMP

ASAHI KASEI
[AK4643]
„ Receiver-amp Output
FS3-0 bits _0,000
(Addr:05H, D5&D2-0)
(1)
RCV bit
(Addr:21H, D0)
DACL bit
(Addr:02H, D4)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMMIN bit
(Addr:00H, D5)
PMLO bit
(Addr:00H, D3)
LOPS bit
(Addr:03H, D6)
RCP pin
(2)
(3)
E1H
18H
(5)
(6)
(7)
(8)
(4)
Hi-Z
1,111
91H
28H
(9)
Normal Output
(10)
(11)
Hi-Z
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL = MINL bits = “0”
(1) Addr:05H, Data:27H
(2) Addr:21H, Data:01H
(3) Addr:02H, Data:10H
(4) Addr:03H, Data:40H
(5) Addr:09H & 0CH, Data:91H
(6) Addr:0AH & 0DH, Data:28H
(7) Addr:00H, Data:6CH
(8) Addr:03H, Data:00H
Playback
(9) Addr:03H, Data:40H
(10) Addr:02H, Data:00H
RCN pin
Hi-Z
VCOM Normal Output VCOM Hi-Z
(11) Addr:00H, Data:40H
Figure 88. Receiver-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4643 is PLL mode, DAC and Receiver-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ RCV-Amp and Power-save mode”: DACL=LOPS bit = “0” Æ “1”
(3) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(4) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
(5) Power Up of DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC
output reflects the digital input data after the initialization cycle (1059/fs=24ms@fs=44.1kHz) is complete.
When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle.
(6) Exit the power-save-mode of Receiver-Amp: LOPS bit = “1” → “0”
(7) Enter the power-save-mode of Receiver-Amp: LOPS bit = “0” → “1”
(8) Disable the path of “DAC Æ RCV-Amp”: DACL bit = “1” Æ “0”
(9) Power Down DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0”
MS0476-E-01
- 99 -
2006/10