AK4643 Datasheet, PDF (89/104 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/RCV/SPK-AMP

ASAHI KASEI
[AK4643]
CONTROL SEQUENCE
„ Clock Set up
When ADC or DAC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
MCKI pin
(1)
(2) (3)
(4)
(5)
Input
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
M/S bit
(Addr:01H, D3)
BICK pin
LRCK pin
MCKO pin
40msec(max)
40msec(max)
(7)
(6)
Output
(8)
Output
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
MCKO, BICK and LRCK output
Figure 78. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4643.
(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power UpVCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(6) The AK4643 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
MS0476-E-01
- 89 -
2006/10