AK4643 Datasheet, PDF (17/104 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/RCV/SPK-AMP

ASAHI KASEI
[AK4643]
Parameter
Symbol
min
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I²C Bus mode):
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
50
tCSH
50
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 39)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Capacitive Load on Bus
Cb
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Power-down & Reset Timing
PDN Pulse Width (Note 40)
tPD
150
PMADL or PMADR “↑” to SDTO valid (Note 41)
tPDV
-
Note 38. I²C is a registered trademark of Philips Semiconductors.
Note 39. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 40. The AK4643 can be reset by the PDN pin = “L”.
Note 41. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1059
max
Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
400
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
0.3
µs
0.3
µs
400
pF
50
ns
-
ns
-
1/fs
MS0476-E-01
- 17 -
2006/10