AK4643 Datasheet, PDF (95/104 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/RCV/SPK-AMP

ASAHI KASEI
[AK4643]
„ Speaker-amp Output
FS3-0 bits _0,000
(Addr:05H, D5&D2-0)
DACS bit
(Addr:02H, D5)
(1)
(2)
1,111
SPKG1-0 bits
(Addr:03H, D4-3)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
00
00H
E1H
(3)
(4)
(5)
01
3CH
C1H
ALC Control 3
(Addr:0BH)
ALC bit
(Addr:07H, D5)
00H
0
(6)
(7)
00H
1
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
E1H
18H
(8)
(9)
91H
28H
PMMIN bit
(Addr:00H, D5)
PMSPK bit
(Addr:00H, D4)
SPPSN bit
(Addr:02H, D7)
SPP pin
(10)
Hi-Z
(11)
(12)
Normal Output
(13)
(14)
Hi-Z
SPN pin
Hi-Z
HVDD/2 Normal Output HVDD/2 Hi-Z
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
ALC: Enable
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:20H
(3) Addr:03H, Data:08H
(4) Addr:06H, Data:3CH
(5) Addr:08H, Data:E1H
(6) Addr:0BH, Data:00H
(7) Addr:07H, Data:20H
(8) Addr:09H & 0CH, Data:91H
(9) Addr:0AH & 0DH, Data:28H
(10) Addr:00H, Data:74H
(11) Addr:02H, Data:A0H
Playback
(12) Addr:02H, Data:20H
(13) Addr:02H, Data:00H
(14) Addr:00H, Data:40H
Figure 84. Speaker-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4643 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ SPK-Amp”: DACS bit = “0” Æ “1”
(3) SPK-Amp gain setting: SPKG1-0 bits = “00” Æ “01”
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 08H)
(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
When PMADL or PMADR bit is “1”, ALC for DAC path is disabled.
(8) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(9) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
(10) Power Up of DAC, MIN-Amp and Speaker-Amp: PMDAC = PMMIN = PMSPK bits = “0” → “1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC
output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is
“1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by
IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC
operation starts from the gain set by IVL/R7-0 bits.
(11) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(12) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”
(13) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” Æ “0”
(14) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMMIN = PMSPK bits = “1” → “0”
MS0476-E-01
- 95 -
2006/10